Gate-all-around transistor (GAAFET)
Also known as: GAAFET, GAA transistor, nanosheet transistor, RibbonFET, MBCFET, gate-all-around
A gate-all-around field-effect transistor (GAAFET) is a transistor design in which the gate, the part that switches current on and off, surrounds the channel on all sides.
It's replacing the FinFET design used since the early 2010s at the most advanced process nodes. While the change sounds incremental, it's the biggest shift in transistor structure in more than a decade, needed because FinFETs were running out of control at tiny sizes.
Gate-all-around transistor (GAAFET), explained at three levels
At home
Picture a garden hose. Pinch it with two fingers on one side and some water still leaks past. Wrap your whole hand around it and you can shut it off completely. A transistor is a tiny switch where a part called the gate pinches off electric current flowing through a channel. In a gate-all-around transistor, the gate wraps the channel on every side, so the switch shuts off fully and wastes less power.
At work
A gate-all-around transistor, or GAAFET, is the newest transistor design used in leading-edge chips, replacing the FinFET design that dominated from about 2012. Samsung, TSMC, and Intel all use it at their most advanced nodes. For businesses, GAA is one reason new processors can run faster at the same power or last longer on a battery, since better control of each transistor means less wasted electricity.
At home
Every transistor has a channel that current flows through and a gate that turns the flow on or off. In old planar transistors, the gate sat only on top of a flat channel. FinFETs stood the channel up as a thin fin so the gate could cover three sides. GAA transistors slice the channel into a stack of thin horizontal sheets, usually three or four, and surround each one completely. That full wrap stops current leaking when the switch is off, which saves battery.
At work
GAA comes in a few named versions. Samsung calls its design MBCFET, TSMC uses nanosheets at its N2 node, and Intel calls its version RibbonFET in the 18A process. The key design advantage is that sheet width can vary: wider sheets carry more current for speed, narrower ones save power and area. FinFETs only came in whole fins, so designers had coarser choices. The new structure also needs new transistor models and design tools, which adds cost and risk early in a node.
At home
A transistor's quality is often judged by how sharply it switches off. As channels shrink, the voltage on the far end starts pulling current through even when the gate says stop, a problem called short-channel effects. Surrounding the channel gives the gate more control, so off-state leakage drops and chips can run at lower voltages. While speed gains get the headlines, in my opinion the real benefit is for phones and laptops, where idle power drain shapes everyday battery life more than peak speed does.
At work
Building GAA starts with a stack of alternating silicon and silicon-germanium layers. After the stack is patterned, the silicon-germanium is etched away sideways, leaving silicon sheets suspended in space, and gate materials are deposited into the gaps, all at near-atomic precision. Variation in sheet thickness or etch depth hurts yield, so the yield ramp is a key competitive variable between Samsung, TSMC, and Intel. Complementary FETs, or CFETs, which stack n-type and p-type transistors vertically, build directly on this process.
Real-world examples
At home
Thomas noticed that reviews of a new phone highlighted its better battery life even with a faster processor. Reading further, he learned the chip used a new GAA transistor design that leaked less power when idle.
At work
Sophie is a hardware architect at a networking company. When choosing a process for a next-generation chip, she compared a mature FinFET node with a newer GAA node. GAA offered better power efficiency, but she weighed it against higher costs and early yield risk.
How it compares
| feature | Gate-all-around (GAAFET) | FinFET | Planar transistor |
|---|---|---|---|
| Gate coverage | All sides of stacked sheets | Three sides of a fin | Top only |
| Introduced in volume | 2022 (Samsung), 2025 (TSMC) | 2011 to 2012 (Intel) | Decades of use |
| Leakage control | Best | Good | Poor at small sizes |
| Design flexibility | Adjustable sheet widths | Fixed fin widths | Simple |
Each generation wraps the gate further around the channel to keep shrinking transistors usable.
For analysts
New transistor designs bring both performance gains and early-node risk. I'd plan hardware refresh cycles around mature yields rather than launch announcements, since first-generation parts on a new architecture often cost more and ship in limited volumes.
History & origin
Transistors were flat (planar) for decades. As they shrank, current leaked even when 'off,' so Intel introduced the 3D FinFET at its 22-nanometre node in 2011, with products in 2012, and the rest of the industry followed. FinFETs raised a fin of silicon so the gate could wrap around three sides. At around 3 nanometres, that wasn't enough. Samsung began mass production of the first GAA process, at 3 nanometres, in 2022. TSMC moved to nanosheet GAA at its N2 node, with volume production starting in late 2025, and Intel introduced its RibbonFET design in its 18A process. In my view, GAA is a reminder that chip progress now comes from clever structures as much as from smaller dimensions.