Backside power delivery
Also known as: backside power, BSPD, PowerVia, Super Power Rail, backside power delivery network, BSPDN
Backside power delivery is a chip manufacturing technique that moves the wires supplying power to transistors from the top of the chip to the underside.
Traditionally, power and signal wires were crammed into the same layers above the transistors. While it sounds like rearranging cables, separating them reduces congestion and voltage loss, and it's one of the biggest changes to chip construction in decades.
Backside power delivery, explained at three levels
At home
Imagine a city where water pipes and fibre cables share the same narrow streets above ground, so crews constantly fight for space. Moving the water mains underground frees the streets for data. A chip has the same layout problem: power wires and signal wires share the wiring layers above the transistors. Backside power delivery moves the power wires underneath, so signals get more room and power arrives with less loss.
At work
Backside power delivery is a chipmaking technique that feeds electricity to transistors from the underside of the chip instead of through the wiring layers on top. Intel's version is called PowerVia, and TSMC's is Super Power Rail. Businesses care because it helps new processors deliver more performance per watt, which adds up to lower electricity bills across laptops and data centres.
At home
A chip is built like a layered cake: transistors at the bottom, then a dozen or more layers of copper wiring above them. Traditionally, power entered from the top and travelled down through all those layers, squeezing through thinner and thinner wires and losing voltage along the way, like water pressure dropping in a long, narrow pipe. With backside power, power connects from below through short, thick wires. Transistors get steadier voltage, and the top layers are left free for signals.
At work
Two problems drive the change. The first is IR drop, the voltage lost as current flows through resistive wiring, which forces designers to run chips at higher voltage to compensate. The second is routing congestion: power lines take up a large share of the best wiring tracks, so signals detour and chips grow larger. Moving power to the back eases both, which Intel reported improved cell density and clock speed. Designers need new tools, design rules, and thermal analysis to use it.
At home
The build sequence is the surprising part. Manufacturers make the transistors and signal wiring as usual, then flip the wafer and bond it face-down to a carrier wafer. They grind and polish the original silicon away until only a layer thinner than a micrometre remains, then build the power wiring on that newly exposed back surface. In my view, it's astonishing that this works at all on wafers holding billions of transistors, and it shows how much chip progress now comes from construction methods.
At work
Implementations differ in how close the power reaches the transistor. Intel's PowerVia uses nano through-silicon vias that connect backside power to the transistor layer. TSMC's Super Power Rail, planned for its A16 node, connects directly to each transistor's source and drain, which saves more area but is harder to build. Thermal behaviour changes because the thinned silicon spreads heat differently, and failure analysis gets harder since engineers traditionally probed chips from the back. Early use favours high-performance products where the gains justify the cost.
Real-world examples
At home
Carlos read a review of a new laptop processor that mentioned 'PowerVia.' He learned it meant power wires had been moved to the back of the chip, one reason the new processor used less power than its predecessor at the same speed.
At work
Lena runs energy planning for a data centre operator. When evaluating server upgrades, she found that new processors built with backside power delivery offered better performance per watt, helping justify the refresh through lower electricity costs.
How it compares
| feature | Backside power delivery | Frontside power delivery |
|---|---|---|
| Power wiring location | Underneath the transistors | Above the transistors, shared with signals |
| Routing congestion | Lower | Higher |
| Voltage loss | Lower | Higher |
| Manufacturing complexity | Higher, requires wafer flipping and thinning | Well established |
| First volume use | Intel 18A (early 2026) | Standard for decades |
Backside power separates power from signals for more efficient chips, at the cost of more complex manufacturing.
For analysts
Efficiency gains from manufacturing changes like backside power add up across a data centre. I'd include performance-per-watt comparisons in any server refresh business case, since energy costs often outweigh the hardware price over a system's life.
History & origin
Research labs, including imec in Belgium, spent years developing backside power concepts, with early ideas such as buried power rails. Intel was the first to bring it to high-volume production with PowerVia, which debuted in its 18A process with Panther Lake laptop processors launched in early 2026. TSMC announced its own approach, called Super Power Rail, for its A16 node, planned for production starting in the second half of 2026, and Samsung has its own plans. Because it changes how chips are built from both sides of the wafer, backside power requires new manufacturing steps, such as bonding the wafer to a carrier and thinning it dramatically. In my opinion, backside power is a quiet revolution: few people will ever hear of it, but it may matter as much as the move to gate-all-around transistors.