Chiplet
Also known as: chiplets, multi-chip module, MCM, tile, disaggregated chip design, UCIe
A chiplet is a smaller chip designed to work together with other chiplets inside a single package, so a processor is built from several pieces instead of one large slab of silicon.
While a single giant chip sounds more elegant, chiplets win on economics: small dies are cheaper to make, defects waste less silicon, and different parts can use different manufacturing processes. AMD's success with chiplets helped push the whole industry in this direction.
Chiplet, explained at three levels
At home
Instead of baking one giant cookie, imagine baking several small ones and arranging them on a plate. If one small cookie burns, you only throw that one away. Chiplets work the same way: a processor is made from several small chips, which is cheaper and less wasteful.
At work
Chiplets let chipmakers mix and match parts, like adding more processing cores or memory controllers, without designing an entirely new chip. That helps them offer more product variations faster and at lower cost.
At home
Larger chips are more likely to contain a defect, which can make the whole chip unusable. By splitting a design into smaller chiplets, manufacturers get more working pieces from each wafer. That's one reason high-core-count desktop and server processors became more affordable.
At work
Chiplets allow heterogeneous integration: compute chiplets can use the most advanced (and expensive) process, while input/output or analogue parts use cheaper, mature processes. The trade-off is that communication between chiplets uses more power and adds latency compared with on-chip connections, so packaging and interconnect design become critical.
At home
Chiplets connect through high-density links in the package, using technologies such as silicon interposers, embedded bridges, or stacking. In my opinion, the interconnect is now as important as the transistors, because a chip is only as fast as the slowest link between its pieces.
At work
Key challenges include 'known good die' testing (verifying each chiplet before assembly), thermal management of stacked or dense packages, and standard interfaces. UCIe aims to create an open ecosystem where companies can combine chiplets from different vendors, though most products still use chiplets from a single company. Advanced packaging capacity has become a supply bottleneck in its own right.
Real-world examples
At home
Marcus was comparing desktop processors and noticed that the high-end model had twice the cores of the mid-range one at less than twice the price. He learned it was built from two identical compute chiplets instead of one, which made it cheaper to produce.
At work
Nadia is a product manager at a networking hardware company. Her team chose a chiplet-based design that reused a proven input/output chiplet and paired it with a new compute chiplet. That cut development time and let them launch a year earlier than a monolithic design would have.
How it compares
| feature | Chiplet design | Monolithic chip |
|---|---|---|
| Structure | Several small dies in one package | One large die |
| Manufacturing yield | Higher, since small dies have fewer defects | Lower for very large dies |
| Mix of processes | Yes, each chiplet can use a different process | No, one process for everything |
| Communication | Slower and uses more power between dies | Fastest, all on one die |
| Design flexibility | High, reuse chiplets across products | Lower |
Chiplets trade some speed between dies for big gains in cost and flexibility.
For analysts
Chiplets shift chip value toward packaging and integration. I'd watch advanced packaging capacity as closely as foundry capacity when assessing supply risk, since that's become a bottleneck for AI chips.
History & origin
Multi-chip packages are old, but the modern chiplet era began when AMD launched its first EPYC server processors in 2017, combining several dies in one package, and then its Zen 2 designs in 2019, which separated compute chiplets from a central input/output die. Intel adopted the approach in products such as its Ponte Vecchio data centre GPU, built from dozens of tiles, and later in its client processors. Apple joined two M1 Max dies to create the M1 Ultra in 2022. That same year, an industry group launched the Universal Chiplet Interconnect Express (UCIe) standard to let chiplets from different companies work together. In my view, chiplets are the industry's practical answer to a slowing Moore's Law: if you can't shrink transistors cheaply, combine smaller chips smartly.