Advanced packaging (CoWoS)
Also known as: CoWoS, chip-on-wafer-on-substrate, 2.5D packaging, 3D packaging, heterogeneous integration, EMIB, Foveros
Advanced packaging is the set of techniques that combine multiple chips, such as a processor and stacks of high-bandwidth memory, into one tightly connected package.
TSMC's CoWoS (Chip-on-Wafer-on-Substrate) is the best-known example and is used in most leading AI accelerators. While packaging used to be the unglamorous final step of chipmaking, it's now a strategic bottleneck: in 2023 and 2024, AI chip supply was limited as much by packaging capacity as by chip manufacturing itself.
Advanced packaging (CoWoS), explained at three levels
At home
Packaging is how chips get combined and connected. Imagine putting a processor and its memory on the same tiny circuit board, so close they can talk almost instantly. Advanced packaging does that, which is why AI chips can move data so fast.
At work
Advanced packaging determines how many high-end chips can be produced. Even if a foundry can make the processor, a shortage of packaging capacity can limit how many finished AI accelerators reach customers.
At home
In CoWoS, chips sit on a thin slice of silicon called an interposer, which contains extremely fine wiring that connects them. That wiring is far denser than a normal circuit board, letting a processor and its memory exchange huge amounts of data with little power.
At work
Packaging approaches include 2.5D (side by side on an interposer or bridge), 3D (stacking chips on top of each other), and fan-out packaging. Each trades cost, density, and thermal performance. For AI accelerators, the package often contains a large compute die and several HBM stacks, making the package one of the most valuable components in a data centre.
At home
Interposers have size limits, set partly by lithography reticle size, so very large packages need variants like CoWoS-L, which uses smaller bridges embedded in an organic layer. In my view, these clever workarounds show how the industry keeps stretching physical limits rather than breaking through them.
At work
Packaging capacity requires specialized equipment, materials, and testing, and it's concentrated in Taiwan, though expansion is underway elsewhere. Thermal management, warpage, and yield of the full package are critical, since one bad component can ruin an assembled unit. Hybrid bonding, which joins chips copper-to-copper without solder bumps, enables much denser 3D stacks and is spreading from memory to logic.
Real-world examples
At home
Fatima read that AI chip shortages weren't just about making the chips but about 'packaging.' She learned that each AI accelerator combined a processor and memory stacks on a silicon interposer, and that only a few factories could do it at scale.
At work
Marcus manages procurement for a cloud provider. When ordering AI servers, the vendor quoted long lead times due to limited CoWoS capacity. Marcus negotiated staggered deliveries and secured part of the order earlier by committing to a longer contract.
How it compares
| feature | 2.5D packaging (CoWoS) | 3D packaging | Traditional packaging |
|---|---|---|---|
| Layout | Chips side by side on an interposer | Chips stacked vertically | Single chip on a substrate |
| Connection density | Very high | Highest | Low |
| Thermal challenge | Moderate | High, heat must escape through layers | Low |
| Typical use | AI accelerators with HBM | Memory stacks, some processors | Most everyday chips |
Advanced packaging trades cost and complexity for much faster connections between chips.
For analysts
If your organization depends on AI hardware, packaging capacity belongs on your supply risk radar. I'd ask vendors directly about packaging lead times, since that's where shortages have appeared first.
History & origin
Traditional packaging simply protected a chip and connected it to a circuit board. As chips grew more complex, 2.5D packaging emerged, placing dies side by side on a silicon interposer with dense connections. TSMC introduced CoWoS in the early 2010s, and it was used in Xilinx FPGAs before becoming central to high-performance GPUs paired with HBM. Intel developed EMIB (embedded bridges) and Foveros (3D stacking), launched in products from the late 2010s. When demand for AI accelerators exploded in 2023, CoWoS capacity became a key constraint, and TSMC rapidly expanded it. Hybrid bonding and 3D stacking are the next steps. In my opinion, packaging has become the place where the chip industry's next decade of progress will happen.