Nanometer Process Node
Also known as: process node, fabrication node, chip process, nm chip, TSMC 3nm, manufacturing node
A nanometer (nm) process node is a label for a generation of chip manufacturing technology.
Originally, the number referred to the minimum feature size (transistor gate length) achievable in that generation -- so a 7nm process could print features 7 nanometers wide. Today, the numbers are marketing labels rather than literal measurements: different foundries use different naming conventions, and the physical dimensions don't match the numbers. What the process node number does indicate reliably: smaller numbers represent newer generations of manufacturing technology that typically enable more transistors per unit area, better performance per watt, and smaller die sizes.
Nanometer Process Node, explained at three levels
At home
When you see a chip described as '3nm' or '4nm,' think of it as a generation label rather than a literal measurement. A '3nm' chip is simply newer and more advanced than a '5nm' chip -- it can fit more transistors in the same space, runs more efficiently, and is typically faster for the same power budget. The actual features on the chip may not be literally 3 nanometers; the number is a naming convention the industry uses. What matters practically: newer (smaller number) process nodes generally mean better performance and battery life in devices like smartphones and laptops.
At work
Process node matters for hardware specification comparisons. When evaluating processor options for any device -- laptop, smartphone, server, embedded system -- the process node indicates which manufacturing generation the chip uses. A processor on a newer node (smaller number) will typically deliver more performance per watt than the same chip design on an older node. For mobile devices and laptops, this translates to battery life. For servers, it translates to energy cost and cooling requirements. Process node is one of the key differentiators when comparing chips released in different years, even if clock speeds appear similar.
At home
Transistor density is the metric that process nodes are most accurately measured by: transistors per square millimeter of die area. TSMC's 5nm node achieves roughly 170 million transistors per mm2; their 3nm node achieves roughly 290 million per mm2. This density improvement enables either: more transistors in the same die area (more capability, more cores, larger caches) or the same transistors in a smaller die area (lower manufacturing cost, smaller package). Both options represent real engineering value, which is why advancing to newer process nodes -- despite the enormous R&D cost -- is economically worthwhile for high-volume chips.
At work
Process node naming across foundries is not standardized, making direct comparisons misleading. Intel's '7nm' (now branded as Intel 4) is comparable to TSMC's '5nm' in transistor density. Samsung's '3nm' (first to use gate-all-around transistors) is comparable to TSMC's '4nm' in practical performance. When comparing chips from Intel, TSMC, and Samsung foundries by process node number, the numbers alone are not directly comparable -- transistor density benchmarks or objective performance benchmarks for the specific workload provide more reliable comparisons than node name alone.
At home
Gate-all-around (GAA) transistors as the successor to FinFET: at 3nm and below, FinFET transistors (where the gate wraps around three sides of the semiconductor channel) are being replaced by gate-all-around (GAA) transistors, where the gate surrounds the channel on all four sides (also called nanosheet FETs or RibbonFETs). GAA provides better gate control, reducing leakage current and enabling further scaling. Samsung first deployed GAA in commercial production at their '3nm' node (2022); TSMC and Intel are deploying GAA at their 2nm/A2 and Intel 20A/18A nodes respectively. GAA is the dominant transistor architecture for sub-3nm process nodes.
At work
Process node cost curve and strategic implications: leading-edge nodes (3nm, 2nm) are extremely expensive per wafer -- TSMC's 3nm wafer cost is estimated at $20,000-25,000, versus roughly $3,000-4,000 for a mature 40nm wafer. This cost structure means leading-edge nodes are only economical for high-value, high-volume chips (smartphone SoCs, high-performance CPUs, AI accelerators). Most of the world's chips by volume are manufactured on mature nodes (28nm-65nm) at much lower cost. The bifurcated market -- leading-edge for high-performance consumer/AI chips, mature nodes for industrial/automotive/cost-sensitive applications -- creates different supply chain dynamics, different vendor relationships, and different technology refresh cycles for each segment.
Real-world examples
At home
Marcus was comparing two laptop processors: one on TSMC's 4nm node and another on Intel's 10nm SuperFin. The spec sheets showed similar clock speeds and core counts. He researched the process nodes: TSMC's 4nm has significantly higher transistor density than Intel's 10nm SuperFin, meaning the TSMC chip could accomplish more per watt. Battery life tests confirmed this: the TSMC-built chip laptop lasted 2 hours longer per charge. The process node difference explained the efficiency gap despite similar surface specifications.
At work
Nadia was specifying embedded processors for industrial IoT sensors. The sensor needed to run on battery power for 3 years. She evaluated chips on 28nm vs. 40nm vs. 65nm process nodes -- not the leading-edge 3-5nm nodes used in smartphones. For low-power embedded applications, mature nodes provide a well-understood power envelope, long supply chain stability (mature node fabs have decades of production ahead), and lower cost per unit. The 28nm chip delivered the right combination of processing capability, ultra-low standby power, and supply stability that the 5-year product lifecycle required.
Common confusions
- Many people assume that a chip labeled '3nm' has features that are literally 3 nanometers in size — Modern process node numbers are marketing labels, not physical measurements. The actual transistor gate length in a '3nm' chip may be closer to 12-18nm; the '3nm' label refers to the generation of manufacturing technology relative to previous generations. The naming disconnect began around 14nm (2014) when transistor geometry became three-dimensional (FinFET) and no single dimension captured the technology's capability. Different foundries use different numbering conventions for comparable generations, making cross-foundry comparisons by node number alone unreliable. Transistor density (transistors per mm2) is a more physically meaningful metric for comparing process generations.
- Some assume newer (smaller) process nodes are always better for every application — Leading-edge process nodes offer performance and efficiency benefits but have disadvantages for many applications: much higher cost per wafer, lower initial yields (before manufacturing is fully optimized), limited supply availability (new nodes have constrained capacity before additional capacity comes online), and shorter production lifespans before the node is succeeded. Industrial, automotive, and medical applications typically require chips that will be manufactured continuously for 10-20 years -- mature nodes (28nm, 40nm, 65nm) are more appropriate. For cost-sensitive, low-volume, or long-lifecycle applications, designing on mature nodes is often the correct decision even when leading-edge nodes are available.
For analysts
Process node literacy is useful when advising clients on hardware procurement, product development, or technology vendor evaluation. The practical points: for consumer-facing products (smartphones, laptops, wearables), process node directly affects the key metrics of battery life and performance -- a useful differentiator when comparing competing devices. For industrial or embedded systems, mature process nodes may be more appropriate than chasing the latest generation. And process node is one reason why chip pricing and availability vary: leading-edge node chips cost more and have tighter supply than mature node equivalents.
History & origin
Semiconductor process nodes were originally named after the minimum feature size of the transistors they could produce: 1 micron (1,000nm) in the mid-1980s, 250nm in the late 1990s, 90nm in 2004, 45nm in 2007. The numbers remained meaningful until approximately the 14nm node (around 2014), when transistor geometry became so complex (3D FinFET structures) that no single dimension captured the technology generation. After 14nm, node naming became increasingly disconnected from physical reality: Intel's '10nm' and TSMC's '7nm' were comparable generations, but the names suggested a gap. Today, TSMC's '3nm' node is more accurately described as the generation after 5nm, and its physical features are not literally 3 nanometers. The industry continues using nm numbers because they provide a relative ordering of technology generations even though the absolute numbers are no longer physically meaningful.